Vendor: Cadence Design Systems, Inc. Category: Smartcard

Simulation VIP for JTAG

The Cadence® JTAG Verification IP provides support for the JTAG protocol specification.

Verification IP View all specifications

Overview

The Cadence® JTAG Verification IP provides support for the JTAG protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. JTAG VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

JTAG standard defines test logic that can be included in an integrated circuit to provide standardized approaches to:

The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).

Supported Specification: JTAG Specification IEEE Std 1149.1-2013.

Key features

  • Multiple subordinates
    • Supports multiple subordinates. Parallel/serial configuration is supported
  • Instructions
    • Supports all standard defined instructions
  • Clamp
    • Optional instruction CLAMP is supported
  • High Z
    • Optional instruction HIGHZ is supported
  • Extest
    • Optional instruction EXTEST is supported
  • Extest Pulse
    • Optional instruction EXTEST_PULSE is supported (from 1149.6 standard)
  • Extest Train
    • Optional instruction EXTEST_TRAIN is supported (from 1149.6 standard)
  • Instruction Length
    • Instruction length is configurable
  • Instruction Codes
    • Instruction codes are configurable

Block Diagram

Simulation VIP for JTAG block diagram

Specifications

Identity

Part Number
Simulation VIP for JTAG
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Smartcard IP cores

What is Simulation VIP for JTAG?

Simulation VIP for JTAG is a Smartcard IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Smartcard?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Smartcard IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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