The Cadence® JTAG Verification IP provides support for the JTAG protocol specification.
The Cadence® JTAG Verification IP provides support for the JTAG protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. JTAG VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.
JTAG standard defines test logic that can be included in an integrated circuit to provide standardized approaches to:
The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).
Supported Specification: JTAG Specification IEEE Std 1149.1-2013.
Note: some files may require an NDA depending on provider policy.
Simulation VIP for JTAG is a Smartcard IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Smartcard IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.