SLVS-EC Verification IP

SLVS-EC is a high-speed serial communication protocol developed by Japan Industrial Imaging Association Standard to support the video data between CMOS Image Sensor(CIS) and Digital Signal Processor(DSP). SLVS-EC VIP can be used to verify Transmitter or Receiver device following the SLVS-EC basic protocol as defined in SLVS-EC.

SLVS-EC Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SLVS-EC Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Full SLVS-EC transmitter device and receiver device functionality.
• SLVS-EC supports version 2.0 specification.
• Supports the following system topologies between CIS and DSP
• Basic Topology
• Multiple I/F Topology
• Multiple CIS Topology
• Supports the following frame synchronization scheme.
• DSP Master with shared clock
• DSP Master without shared clock
• CIS Master with shared clock
• CIS Master without shared clock
• Supports the following Baud Rates,
• Baud Grade 1 with Baud Rates of 1152 to 1250 Mbps
• Baud Grade 2 with Baud Rates of 2304 to 2500 Mbps
• Baud Grade 3 with Baud Rates of 4608 to 5000 Mbps
• Supports multi lanes upto 8 lanes(1,2,4,6,8 lanes).
• Supports RAW 8,10,12,14,16 bit color format.
• Supports Embedded data transfer.
• Supports Multiple stream transfer
• Supports LINK Protocol Management.
• Supports PHY Protocol Management.
• Supports 8B10B encoding / decoding.
• Supports Forward Error Correction (FEC).
• Supports Error Correction Code(ECC) and Cyclic Redundancy Check(CRC)
• Supports skew insertion.
• Supports Jitter insertion.
• Detects and reports the following errors,
• Invalid control character
• Disparity error
• Invalid 10bit code
• Sync errors
• Truncated Packet
• Illegal Standby /Config
• Insufficient Blanking
• Delayed Line End
• Line Boundary Error
• Bandwidth Misarrangement
• Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Status counters for various events on bus.
• Callbacks in node transmitter, receiver and monitor for user processing of data.
• SLVS-EC Verification IP comes with complete testsuite to test every feature of SLVS-EC version 2.0 specifications.
• Functional coverage for complete SLVS-EC features.

• Faster testbench development and more complete verification of SLVS-EC designs.
• Easy to use command interface simplifies testbench control and configuration of receiver and transmitter.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the SLVS-EC testcases.
• Examples showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.