SLVS-EC TRANSMITTER IIP

SLVS-EC Transmitter core is compliant with standard SLVS_EC specification as 2.0. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. SLVS-EC Transmitter IIP is proven in FPGA environment.The host interface of the SLVS-EC can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

SLVS-EC TRANSMITTER IIP is supported natively in Verilog and VHDL

• Compliant with SLVS-EC specification 2.0.
• Full SLVS-EC transmit functionality.
• Supports the following system topologies between CIS and DSP
• Basic Topology
• Multiple I/F Topology
• Multiple CIS Topology
• Supports the following frame synchronization schemes.
• CIS Master with shared clock
• CIS Master without shared clock
• Supports the following Baud Grades,
• Baud Grade 1 with Baud Rates of 1152 to 1250 Mbps
• Baud Grade 2 with Baud Rates of 2304 to 2500 Mbps
• Baud Grade 3 with Baud Rates of 4608 to 5000 Mbps
• Supports lanes upto 8 lanes(1,2,4,6,8 lanes).
• Supports the following color formats.
• RAW 8
• RAW 10
• RAW 12
• RAW 14
• RAW 16
• Supports Embedded data transfer.
• Supports Multiple stream transfer.
• Supports LINK Protocol Management.
• Supports PHY Protocol Management.
• Supports 8B10B Encoding .
• Supports Error Correction Code(ECC).
• Supports Cyclic Redundancy Check(CRC).
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The SLVS-EC Transmitter interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.