Overview
In production since 2011.
This Cadence® Verification IP (VIP) supports the IBM PLB standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for PLB is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. The PLB VIP supports DCR, PLB4, and PLB6, for core, devices, and bus controller.
Supported specification: PLB4 and PLB6 Specifications - IBM confidential.
Learn more about Protocol Bridge IP core
Cadence has successfully demonstrated first-pass silicon success of its UCIe™ standard package IP on Samsung Foundry's 5nm automotive process. This milestone underscores Cadence's commitment to delivering high-performance, automotive-grade IP solutions that meet the stringent requirements of next-generation automotive and high-performance computing applications.
Ethernet was originally designed for high-speed data transfer and interoperability between devices. However, traditional Ethernet does not provide built-in mechanisms for securing data traffic, such as encryption or authenticity protection. This is where MACsec comes into the picture.
When a new interface technology emerges, specs and simulations are only part of the story. What customers and partners truly need is confidence that the ecosystem can work, in practice, across chips, controllers, PHYs, platforms, and devices.
Far from just a functional piece of hardware, PCIe switches are the invisible foundation that accelerates data processing, eliminates bottlenecks, and ensures modern AI systems operate with blazing speed and pinpoint precision.
Cadence's industry-first eUSB2V2 IP, built on the advanced TSMC N3P process and compliant with the latest embedded USB2 Version 2 standard, transforms computing devices by delivering unprecedented capabilities for laptops, AI video devices, and advanced image signal processor (ISP) systems.
To meet the safety and deterministic latency requirements for controlling a car, a new set of open standards is being developed, collectively referred to as “Time Sensitive Networking,” or TSN. These improve the reliability, timing, redundancy, and failure detection ability of Ethernet to the level where it can be applied throughout an automobile. This article describes how Cadence has addressed the hardware requirements of TSN in its Automotive Ethernet Media Access Controller (MAC).
