Vendor: SmartDV Category: JESD204

JESD207 Verification IP

The SmartDV's JESD207 verifies the Radio Front end-Baseband digital parallel interface.JESD207 Verification IP can be used to ver…

Verification IP View all specifications

Overview

The SmartDV's JESD207 verifies the Radio Front end-Baseband digital parallel interface.JESD207 Verification IP can be used to verify BBIC or RFIC following the JESD207 basic protocol as defined in JESD207 and provides the following features.

JESD207 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

JESD207 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports JESD207 specification.
  • Operates as BBIC (Baseband IC) and RFIC (Radio front end IC) monitor.
  • Supports half duplex data transfer.
  • Supports DDR source synchronous data transfer timing.
  • Supports both data path transaction and control plane transactions.
  • Supports multiple parallel sample streams in BBIC and RFIC data path interface.
  • Supports data path transaction
    • Supports transmit burst and receive burst
    • Supports both 10 bits and 12 bits sample width
    • Supports 2 way interleave and 4 way interleave transactions
    • Supports 1T1R,1T2R,2T2R systems
  • Supports control plane transaction
    • Supports 4 wires write and 4 wires read
    • Supports 3 wires write and 3 wires read
    • 1bit command plus 7bit address control field format
    • Serial clock can be stopped between transactions for reducing control plane power consumption to negligible levels
    • Extended data tranactions
  • Supports various kinds of errors
    • Mixed data error
    • Invalid address error
  • Status counters for various events on bus.
  • Supports constraints randomization.
  • Built in functional coverage analysis.
  • Callbacks in BBIC and RFIC for various events.
  • Test suite to test each and every feature of JESD207 specification.

Block Diagram

JESD207 VIP block diagram

Benefits

  • Faster test bench development and more complete verification of JESD207 designs.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
  • Easy to use command interface simplifies testbench control and configuration of BBIC and RFIC.
  • Comes with complete test suite to test each and every feature of JESD207.

What’s Included?

  • Complete regression suite containing all the JESD207 testcases.
  • Examples showing how to connect various components,and usage of BBIC,RFIC and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
JESD207 VIP
Vendor
SmartDV
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about JESD204 IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about JESD204 IP cores

What is JESD207 Verification IP?

JESD207 Verification IP is a JESD204 IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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