DDR3 Monitor Verification IP

DDR3 Monitor provides an smart way to verify the DDR3 component of a SOC or a ASIC. The SmartDV's DDR3 Monitor is fully compliant with standard DDR3 Specification and provides the following features.

DDR3 Monitor Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR3 Monitor Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports DDR3 memory devices from all leading vendors
• Quickly validates the implementation of the DDR3 standard
• Constantly monitors DDR3 behavior during simulation
• Checks for following
• Check-points include Initialization rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• Support for full-timing as well as behavioral versions in one model
• Support for all timing delay ranges in one model: min, typical and max
• Built in coverage analysis
• Supports Callbacks, so that user can access the data observed by monitor.

• Faster testbench development and more complete verification of DDR3 designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the DDR3 testcases.
• Examples showing how to connect and usage of Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.