Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: PLL

SIMC 65nm LL 2.5v Audio PLL

This PLL is designed for audio clock generation.

Overview

This PLL is designed for audio clock generation. The reference clock is 12MHz, 13.5MHz or 19.2MHz, which can be either from the crystal OSC or from internal clock source. It supports 256*fs and 128*fs clock outputs, where fs is the audio system sample rate of 8k/11k/12k/16k/22k/24k/32kHz/44.1kHz/48kHz/192k. The IP integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.

Key features

  • Process: SMIC 65nm LL 1.2v/1.8v/2.5v 1P8M CMOS Logic process Supply voltage: 1.2v +/-10%; 2.5v +/-10%
  • Reference input: 12MHz, 13.5MHz or 19.2MHz
  • Clock output: 24.572MHz, 12.286MHz, 11.294MHz, 8.190MHz, 6.143MHz, 5.647MHz, 4.095MHz, 3.071MHz, 2.823MHz, 2.048MHz
  • Output duty cycle: 45~55%
  • Current: <3.5mA
  • Operating temperature: -40~125°C

Specifications

Identity

Part Number
S65LLV25_PLL_05
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Frequently asked questions about PLL IP cores

What is SIMC 65nm LL 2.5v Audio PLL?

SIMC 65nm LL 2.5v Audio PLL is a PLL IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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