Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

SD/EMMC PHY

Physical Layer Interface for SD and eMMC Storage Devices

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Overview

The SD/eMMC PHY provides the physical interface between the digital controller and external memory storage, such as SD cards or eMMC chips. The PHY includes delayline, DigiLogic, and high speed IO which are compliant with SD/eMMC protocol. The SD/eMMC PHY I/O signal voltage is within 3.3V/1.8V. This IP supports SD3.1 and eMMC5.1, including dual data rate for DDR50 and HS400, and single data rate for SDR104 and HS200.

Key features

  • DLL_CLK frequency : 50 MHz to 208 MHz
  • SD operation modes: DS, HS, DDR50, SDR50, and SDR104
  • eMMC bus modes: HS200 and HS400
  • Type: 1 bi-directional CLK + 1 bi-directional CMD + 8 bi-directional DATA channel
  • IO driver supports 33/50/66/100Ω terminations
  • Power Supply:
    • Digital supply: 0.72 V to 0.88 V
    • Analog supply: 2.97 V to 3.63 V
  • Operating junction temperature: -40°C~125°C

Block Diagram

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Specifications

Identity

Part Number
SD/EMMC PHY
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Controller / PHY
PHY

Files

Product Sheet Download

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Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is SD/EMMC PHY?

SD/EMMC PHY is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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