RoE Verification IP
RoE Verification IP is compliant with IEEE 1914.3-2018 for Radio over Ethernet Encapsulations and Mappings and IEEE 802.3 Specifi…
Overview
RoE Verification IP is compliant with IEEE 1914.3-2018 for Radio over Ethernet Encapsulations and Mappings and IEEE 802.3 Specification. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment.
RoE Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
RoE Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports IEEE 1914.3-2018 for Radio over Ethernet Encapsulations and Mappings and IEEE 802.3 Specification
- Supports Encapsulation and de-encapsulation functions and locations
- Supports Encapsulation transport format
- Supports RoE mappers/RoE de-mappers upto 256
- Supports the mapping of each I/Q Data sample
- Supports Control and Management data transfer.
- Supports the following RoE sub types
- RoE control subtype
- RoE structure-agnostic data subtype
- RoE structure-aware CPRI data subtype
- RoE Slow C&M CPRI subtype
- Native RoE time domain data subtype
- Native RoE frequency domain data subtype
- RoE native PRACH data subtype
- Supports bus accurate timing and timing checks.
- Supports Ethernet 10G/25G/40G/50G/100G/200G and 400G Ethernet Speeds
- Supports Glitch insertion and detection
- Supports all types of TX and RX errors insertion/detection at each layer.
- Comes with Tx BFM, Rx BFM, and Monitor
- Supports Pause frame generation and detection
- Callbacks in master and slave for various events
- Status counters for various events in bus
- Supports insertion of scrambler errors.
- Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Supports constraints Randomization.
- RoE Verification IP comes with complete test suite to test every feature of RoE specification.
- Functional coverage for complete RoE features.
Block Diagram
Benefits
- Faster testbench development and more complete verification of RoE designs
- Easy to use command interface simplifies testbench control and configuration of TX and RX
- Simplifies results analysis
- Runs in every major simulation environment
What’s Included?
- Complete regression suite (UNH) containing all the RoE testcases.
- Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Ethernet IP cores
What is RoE Verification IP?
RoE Verification IP is a Ethernet IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.