Overview
The SiFive Performance™ P400-Series application processors are SiFive’s first efficiency-focused Out-of-Order processors. The P400-series is derived from the successful and mature P500-Series, with considerable finely-tuned optimizations for best-in-class performance efficiency and compute density.
The P470 vector application processor, with a 128-bit RISC-V Vector ALU, is capable of 2x the single thread performance of an Arm Cortex-A55, achieving >8 SpecINT2k6/GHz, still within similar area and power budgets, representing a significant upgrade to legacy efficiency class cores currently available.
For applications that don't require vector compute, or for more area-constrained markets, the P450 offers similar performance levels in a smaller area footprint.
Learn more about CPU IP core
How embedded RISC-V processors in NICs, retimers, optics, switches, and security chips are overcoming modern scaling limits
How programmable RISC-V solutions optimize, control and direct custom accelerator functionality, unlocking the next generation of AI performance with SiFive intelligent control.
In a demonstration-only system, the companies showed the ability to run the modern Gemma4-E2B LLM model using ROCm 10.0 on SiFive servers powered by the SiFive Performance™ P870-D CPUs acting as the head node, and AMD Radeon™ AI PRO R9700 GPUs driving the inference offload.
The broader RISC-V standards process continues to deliver innovation that responds dynamically to evolving market needs. If you didn’t see the announcement, in an important milestone for the open hardware ecosystem, the RISC-V Board of Directors officially ratified the S-mode Physical Memory Protection (SPMP) version 1.0 specification on August 20, 2026.
Powered by SiFive’s latest RISC-V CPU technology, the new development platform enables hands-on software porting, workload tuning, and validation testing for hyperscaler customers and ecosystem partners
We’re thrilled to announce the launch of the SiFive Kernel Library or SKL (pronounced “skill”), an open-source collection of highly-optimized computational routines for the RISC-V Vector ISA (RVV) and its various extensions, including SiFive’s matrix engines.