DDR Interface IP cores provide the controller, PHY, and calibration technologies required to connect SoCs and ASICs to external DRAM memory devices, enabling high-bandwidth and low-latency memory access for compute-intensive applications.
This category includes IP solutions supporting DDR2, DDR3, DDR4, and DDR5 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, training engines, initialization logic, timing management, ECC support, and signal integrity optimization features designed for reliable operation across advanced semiconductor process nodes.
TSMC CLN16FFCLL 16nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLL 16nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLL 16nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
High Performance DDR 3/2 Memory Controller IP
This memory controller supports DDR2/3 SDRAM.
DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
The DDR (Double Data Rate) controller IP is for LPDDR4 and DDR4/3/3L optimized for low latency.
DDR 4/3 Memory Controller IP - 2400MHz
This memory controller supports DDR3/4 SDRAM.
The DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, provides the industry's highest data rates combined with low-latency throughput.
1 Gbps DDR rail to rail LVDS receiver
LVDS_RX is LVDS receiver with rail to rail input range.
065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmit…
1.6 Gbps DDR Programmable LVDS Transmitter/Receiver
090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias.
Truechip's Verification IP (VIP) for DFI provides an effective and efficient way to verify the components interfacing with the DFI interface of an ASIC/FPGA or SoC.
The DDR6 Verification IP provides an effective & efficient way to verify the components interfacing with DDR6 interface of an ASI…
High-Performance SPI Master/Slave with HyperBus™ & xSPI Support The HyperBus™ Memory Controller IP Core is a high-speed, fully co…
MRDIMM DDR5 & DDR5/4 PHY & Controller
The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring acces…