HYPERBUS™ Memory Controller

High-Performance SPI Master/Slave with HyperBus™ & xSPI Support

The HyperBus™ Memory Controller IP Core is a high-speed, fully configurable SPI master/slave solution, designed for seamless integration into modern SoC and FPGA architectures. Building on the proven DFSPI core, this IP bridges easily to APB, AHB, and AXI buses, supporting SINGLE, DUAL, QUAD, and OCTAL SPI modes for maximum design flexibility.

Optimized for HyperBus™ memory and xSPI (JESD251A) standards, the controller enables high-performance communication with HyperRAM™ and NOR/NAND Flash memories. Designers benefit from fine-grained control over serial clock polarity and phase (SCK), ensuring compatibility with a wide range of SPI peripherals.

This high-speed HyperBus™ memory controller IP Core provides reliable, low-pin-count memory access for embedded applications, high-performance SoCs, and FPGA-based designs. With DCD-SEMI’s emphasis on robust, standards-compliant IP cores, developers can achieve maximum throughput, flexibility, and integration ease for memory-intensive systems.

Ideal for designs requiring a HyperBus memory controller IP package, this IP core simplifies communication with popular SPI Flash memories while offering robust support for high-speed, low-pin-count HyperRAM™ devices. Backed by DCD-SEMI’s reliability and customization flexibility, this IP core ensures optimal performance across a wide range of applications.

• NOR & NAND Flash Memory Support
• Set of software-accessible control registers to execute any Flash memory command
• Supports any device clock frequency, polarity, and phase,
• Programmable baud rate generator,
• Built-in FLASH Commands decoder supports most popular FLASH devices,
• Optional built-in AES Encoder/Decoder
• DMA support
• Optional support for various SPI Bus Standards: HyperBus^TM, xSPI
• Compliant with AMBA2 Specification, support APB, AHB, AXI bus interfaces
• Single, Dual, Quad and OCTAL SPI transfer/reception
• Execute in place – XIP functionality support
• Data Bus Size configuration to 8, 16, or 32 bits wide
• Optional FIFO size extension
• Maximum supported Flash address range – 32 bits
• Up to 4 SPI slaves can be addressed
  • Software Slave Select Output – SSO – selection
  • Automatic Slave Select outputs assertion
• System error detection
• Interrupt generation
• Bit rates are generated as 1/ 2.. 1/255 of the system clock.
• Four SPI transfer formats supported: CPOL/CPHA.
• A simple interface allows easy connection to microcontrollers
• Fully synthesizable, static synchronous design with no internal tri-states

• HyperBus™ and xSPI support for next-generation memory interfaces
• Flexible SPI modes: SINGLE, DUAL, QUAD, OCTAL
• Bridges APB, AHB, AXI buses for easy SoC integration
• Fully programmable SCK parameters for custom clocking requirements
• Automatic Slave Select control via SSCR register
• Technology-independent HDL design deployable on ASIC and FPGA
• DMA support with single and multi-transfer modes for low-latency operation
• Customizable configuration tailored to system design needs

•  HDL Source Code
•  Testbench environment
  •  Automatic Simulation macros
  •  Tests with reference responses
•  Synthesis scripts
•  Technical documentation
•  12 months of technical support