The MACSEC-MG IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports the AES-GCM and AES-GCM-XPN cipher suites provisioned by the MACsec standard and the VLAN-in-Clear improvement. The engine is silicon- and performance-optimized for networks operating from 2.5 Gbps to 10 Gbps and beyond; up to 16.75 Gbps is possible with this core.
Featuring a configurable number of Security Associations (up to 64k), this protocol engine supports multiple security channels and can implement multiple Security Entities (SecYs). It operates in full-duplex mode at line speed in each direction for 2.5 Gbps to 16.75 Gbps connections. It does so by implementing a 128-bit wide data path, which provides adequate performance while minimizing silicon resources.
Designed for ease of integration, the MACSEC-MG core is a fully synchronous, single-clock domain design that uses standardized interfaces and can be optionally pre-integrated with companion cores available from CAST.
The control and status registers (CSR) of the core are accessible via a generic 32-bit memory-mapped slave interface. Interface bridges delivered with the core can convert this generic host interface to a 32-bit AMBA® APB or AHB-Lite, Avalon®-MM, or Wishbone interface. Packet data are input and output via AXI Stream interfaces with configurable data width, or optional XGMII bridges, enabling direct connection to Ethernet MACs, PHYs, PTP timestamping units, or other higher-layer protocol engines. The core can be delivered pre-integrated with the Low-Latency Ethernet MAC, PHY-side and MAC-side XGMII bridges, or any Ethernet TSN cores available from CAST.
