LPC Verification IP
The LPC Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC.
Overview
The LPC Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC. The LPC VIP is fully compliant with LPC Specification version 1.1 The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time.
Key features
- Compliant with LPC 1.1 specifications
- Supports the following operations
- Memory Read and Write
- Bus Master Memory Read and Write
- I/O Read and Write
- Bus Master I/O Read and Write
- Firmware Memory Write and Read
- DMA read and write
- Supports bandwidth up to 33Mhz
- Host and Device support all LPC transactions
- Supports Power State transaction
- Supports Wake up transaction
- Supports LDRQ and Sync Rules
- Support for interrupts
- Support for wait states
- Callbacks for error injections
- Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing, and protocol violations.
- In-built coverage analysis
- LPC VIP comes with a complete test suite to verify every feature
- LPC VIP comes with a Transaction analyzer and Performance Monitors
Block Diagram
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure the highest levels of quality.
- Availability of various Regression Test Suites.
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity examples for all the components.
- Consistency of interface, installation, operation, and documentation across all our VIPs.
- Provide complete solutions and easy integration in IP and SoC environments.
What’s Included?
- LPC Host and LPC Device BFM
- LPC Monitor
- LPC Scoreboard
- Testbench Configurations
- Test Suite (Available in Source code)
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about LPC IP core
Serial Peripheral Interface. SPI, these three letters denote everything you asked for
Low Power Design in SoC Using Arm IP
Increasing bandwidth to 128 GB/s with a tailored PCIe 6.0 IP Controller
Ultra HD H.264 Video Codec IP solution on Zynq FPGA
ATPG Challenges at Lower Technology Nodes
Frequently asked questions about LPC IP cores
What is LPC Verification IP?
LPC Verification IP is a LPC IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this LPC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.