LPC Verification IP
LPC (Low Pin Count Interface) Verification IP provides an smart way to verify the LPC bi-directional bus.
Overview
LPC (Low Pin Count Interface) Verification IP provides an smart way to verify the LPC bi-directional bus. The SmartDV's LPC Verification IP is fully compliant with version 1.1 of the LPC Specification and provides the following features.
LPC Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
LPC Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Compliant to LPC 1.1 specifications.
- Supports bandwidth up to 33 MHz.
- Supports the following operations.
- Memory read and write
- I/O read and write
- DMA read and write
- Bus Master memory read and write
- Bus Master I/O read and write
- Firmware memory read and write
- Host is capable of generating all types of LPC transactions.
- Device is capable of responding to all types of LPC transactions.
- Supports LDRQ Request.
- Supports Serial Interrupts.
- Supports variable number of wait states
- Supports Wakeup and Power state transactions.
- Supports insertion of various types of errors.
- Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
- LPC Verification IP comes with complete testsuite to verify each and every feature of LPC specification.
- LPC monitor has built in coverage analysis.
- LPC monitor checks for protocol errors and timing violations.
Block Diagram
Benefits
- Faster testbench development and more complete verification of LPC designs.
- Easy to use command interface simplifies testbench control and configuration of Host and Device.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the LPC testcases to certify LPC Host and Device.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about LPC IP cores
What is LPC Verification IP?
LPC Verification IP is a LPC IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this LPC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.