LPC Assertion IP

LPC Assertion IP provides an efficient and smart way to verify the LPC designs quickly without a testbench. The SmartDV's LPC Assertion IP is fully compliant with standard LPC Specification and provides the following features.

LPC Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPC Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Specification Compliance
  • Compliant to LPC 1.1 specifications.
  • Supports bandwidth upto 33 MHz.
  • Supports the following operations
  • Memory read and write
  • I/O read/write
  • DMA read/write
  • Bus Master memory read/writ0065
  • Bus Master I/O read/Write
  • Frimware memory read/write
  • Supports variable number of wait_states
  • Supports Wakeup and Power state transactions.
• Assertion IP features
  • Assertion IP includes:
  • System Verilog assertions
  • System Verilog assumptions
  • System Verilog cover properties
  • Synthesizable Verilog Auxiliary code
  • Support Master mode, Slave mode, Monitor mode and Constraint mode.
  • Supports Simulation mode (stimulus from SmartDV LPC VIP) and Formal mode (stimulus from Formal tool).
  • Rich set of parameters to configure LPC Assertion IP functionality.

• Runs in every major formal and simulation environment.

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.