Vendor: SmartDV Technologies Category: LPC

LPC Assertion IP

LPC Assertion IP provides an efficient and smart way to verify the LPC designs quickly without a testbench.

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Overview

LPC Assertion IP provides an efficient and smart way to verify the LPC designs quickly without a testbench. The SmartDV's LPC Assertion IP is fully compliant with standard LPC Specification and provides the following features.

LPC Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPC Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Compliant to LPC 1.1 specifications.
    • Supports bandwidth upto 33 MHz.
    • Supports the following operations
    • Memory read and write
    • I/O read/write
    • DMA read/write
    • Bus Master memory read/writ0065
    • Bus Master I/O read/Write
    • Frimware memory read/write
    • Supports variable number of wait_states
    • Supports Wakeup and Power state transactions.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV LPC VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure LPC Assertion IP functionality.

Block Diagram

LPC AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
LPC AIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about LPC IP cores

What is LPC Assertion IP?

LPC Assertion IP is a LPC IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this LPC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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