USB 3.0 femtoPHY in UMC (28nm, 12nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a physical (PHY) layer IP solution for low-power mobile an…
- USB 3.0
- UMC
- 28nm
- Available on request
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB 3.0 femtoPHY in UMC (28nm, 12nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a physical (PHY) layer IP solution for low-power mobile an…
USB 3.0 femtoPHY in TSMC (28nm, 22nm, 16nm, 12nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a physical (PHY) layer IP solution for low-power mobile an…
USB 3.0 femtoPHY in Samsung (14nm, 11nm, 10nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a physical (PHY) layer IP solution for low-power mobile an…
USB 3.0 femtoPHY in GF (28nm, 12nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a physical (PHY) layer IP solution for low-power mobile an…
USB 2.0 picoPHY in UMC (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…
USB 2.0 picoPHY in TSMC (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 nanoPHY in SMIC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
Precision Time Protocol or PTP or IEEE1588 is one such protocol that allows synchronization of an order of 1us with the master (m…
External Flash Memory Interface IP
Flash memory forms a basic constituent in many FPGA based embedded systems using Xilinx SRAM based FPGAs.
Gigabit Ethernet 802.3 MAC Controller IP
The Giga MAC IP is an embedded Fast Ethernet controller module.
The PCIe 5.0 Controller is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and eas…
The PCIe 5.0 Controller is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and eas…
OPENEDGES On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end i…
USB 2.0 femtoPHY in Samsung (14nm, 11nm, 8nm, 7nm, 5nm, SF4X)
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
The core Implements a UDP/IP hardware protocol stack that enables wire-speed communication over a LAN or a point-to-point connect…
USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, N7, N6, N5, N3P)
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
VESA DSC 1.1 Encoder IP Core for Automotive Displays (ASIL-B Ready ISO 26262 Certified)
The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder.
IQonIC Works I3C Slave Core provides a slave interface for the following protocols: - I2C standard mode (100kbps) - I2C fast mode…