USB3.2 Gen2 x2-lane, Dual-Role PHY, TSMC N6, 1.8V, N/S orientation, type-C
The USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.
Overview
The USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compliant with the PIPE4.0 and UTMI+ specifications. The USB 3.2 Gen2 IP integrates high-speed mixed signal circuits to support Gen2 and Gen1 traffic and is backward compatible with 480Mbps high-speed, 12Mbps full-speed, and 1.5Mbps low-speed data rates. To support USB Type-C connectors, the USB 3.2 Gen2 IP also integrates the active switch to support the bi-directional plug-in and the specific functions (USB attachment cable orientation detection and VBUS configuration) through the CC1/CC2 pins defined in Type-C connector.
Key features
- Worldwide smallest USB 3.2 Gen2 PHY IP (e.g. IP size @28HPC+ is smaller than 0.7mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2 and 2.0 electrical specifications
- Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
- Integrates an active switch to support the orientation-less connection with USB Type-C connectors
- Provides an auxiliary CC module IP to support USB Type-C related functions
- Supports both Wire-bond and flip-chip package types
- Supports internal loop back and BIST functions for mass production testing
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 6nm | N6 | — |
Specifications
Identity
Standards & Interfaces
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Single-Protocol PHY IP
What is USB3.2 Gen2 x2-lane, Dual-Role PHY, TSMC N6, 1.8V, N/S orientation, type-C?
USB3.2 Gen2 x2-lane, Dual-Role PHY, TSMC N6, 1.8V, N/S orientation, type-C is a Single-Protocol PHY IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.