USB Full Speed Transceiver
- Single-Protocol PHY
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB Full Speed Transceiver
Size optimized, Silicon agnostic, Silicon Proven Ethernet PCS IP core for High Speed Ethernet applications The 200G/400G Ethernet…
ONFI 5.0 NAND Fash PHY IP Compliant to JEDEC
Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
Intel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targe…
Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…
40G Ethernet MAC and PHY FPGA IP Core
The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.
1G/10Gb Ethernet PHY Intel® FPGA IP
The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…
Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V LVDS Transceiver.
The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for hi…
OT3910bjc is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to po…
MSquare's eDP PHY is a reliable solution for display interface requirements, supporting resolutions of 4K and higher.
MSquare's ONFI 5.1 PHY is a high-performance and low-power PHY IP, which supports all modes of the Open NAND Flash Interface (ONF…
Our LVDS (Low Voltage Differential Signaling) and OpenLDI (Open Low-voltage Differential Signaling Interface) PHY which is compos…
The HDMI 2.0 TX (Transmitter) is a multimedia interface designed to deliver high-definition video and audio from source devices t…
USB 2.0 nanoPHY - UMC 65SP, OTG
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
USB 2.0 picoPHY - UMC 28HLP18 x1, North/South (vertical) poly orientation
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …