The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
- PCIe Gen6
- TSMC
- 3nm
- N3A
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
PCIe 6.0 PHY, TSMC N6 x4 1.2V, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
LVDS I/O IP - High Frequency Transceiver
The Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data t…
16Gbps and 10Gbps multi-protocol SerDes PHY
224G Ethernet PHY, TSMC N3E x4, North/South (vertical) poly orientation
The 224G Ethernet PHY IP, an integral part of the high-speed SerDes IP portfolio, meets the growing high bandwidth and low latenc…
TSMC N4P SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N5 SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
USB Power Delivery 3.1 Physical Layer
CT20602 is a USB Power Delivery 3.1 Physical Layer.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP
The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 55SP
The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
OPEN Alliance TC6 10BASE-T1S MACPHY Interface
The CT25209 Digital IP core implements the MACPHY SPI protocol defined by the “OPEN Alliance TC6 Serial 10BASE-T1x MACPHY Interfa…
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF
The GPHY is a integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption.
USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 12SF++
A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data …
USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++
A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
Silicon Proven 1G Ethernet PHY IP as Whitebox
1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 supporting…
The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process.
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…