Vendor: Synopsys, Inc. Category: Single-Protocol PHY

10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation

The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…

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PCIe Gen3 TSMC 6nm N6FF View all specifications

Overview

The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.

The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.

The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market.

Key features

  • Supports 1.25 Gbps to 10 Gbps data rates
  • Supports PCI Express 3.1, SATA 6G, SGMII
  • Supports x1 to x16 macro configurations
  • Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design
  • Spread Spectrum Clock (SSC)
  • Separate Reference Clock Independent SSC (SRIS)
  • Reference clock sharing for aggregated macro configurations
  • PCI Express Aggregation and bifurcation
  • Embedded bit error rate (BER) tester and internal eye monitor
  • Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
  • Supports flip chip and wirebond packaging
  • Supports IEEE 1149.6 AC Boundary Scan
  • Supports -40C to 125C Tj

Block Diagram

dwc_c10pcie3phy_tsmc16ffpll_x4ns block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 6nm N6FF —

Specifications

Identity

Part Number
dwc_c10pcie3phy_tsmc16ffpll_x4ns
Vendor
Synopsys, Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
PCIe Gen3

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is 10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation?

10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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