LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver.
- Single-Protocol PHY
- In Production
- Immediate
- IEEE 1596.3 Standard
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver.
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data c…
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash co…
The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA.
Ultra-Low-Latency 10GE PHY+MAC
Having the lowest network latency is critical for Accelerated Finance.
The TRC16024CPA is a four lane Gen 1,2,3,4 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transm…
USB 1.1/2.0 full speed USB PHY
T25201 is a and high integrated USB 2.0 low speed and full speed transceiver implementing the physical layer of a USB compliant d…
Aurora-like 64b/66b @14Gbps for ALTERA Devices
REFLEX CES introduces a release at 14Gbps of its Aurora-like IP Core based on ALTERA FPGA enabling interoperability between XILIN…
Brite provides USB2.0 OTG PHY which is a mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (So…
High-Speed LVDS (SERDES) Transceiver
The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applicatio…
Serial ATA (SATA) PHY Transceiver IP
SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.
PCI Express PIPE PHY Transceiver
SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling.
Integrates MAC IP to a broad range of PHY and SerDes IP
Long reach SerDes for Automotive Sensor and Display Applications
Long Reach SerDes for Automotive Sensor and Display Applications
The embedded USB 2.0 (eUSB2) PHY is a high-speed System-on-Chip (SoC) integrated transceiver IP in process that implements the In…
The Mixel Automotive SerDes Alliance Motion Link (ASA-ML) PHY is a high-speed Automotive SerDes solution compliant with the Autom…
The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.
SD4.x UHSII is PHY IP solution for UHS-II interface for next generation of ultra high speed used in both SDHC and SDXC.