Connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices.
- Network-On-Chip
- March 2014
NoC IP cores (Network-on-Chip IP) are advanced interconnect solutions used in modern SoC and ASIC designs to enable scalable and efficient communication between multiple processing elements, memories, and peripherals.
As system complexity increases, traditional bus-based architectures become inefficient. Network-on-Chip (NoC) architectures provide high-bandwidth, low-latency, and scalable communication, making them essential for AI processors, multicore systems, and high-performance SoCs.
This catalog allows you to compare NoC IP cores from leading vendors based on topology, bandwidth, latency, quality of service (QoS), and process node compatibility.
Whether you are designing a mobile SoC, an AI accelerator, or a data center chip, you can find the right NoC IP to optimize system performance.
Connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices.
Network-on-Chip (NoC) Interconnect IP
Vtool NoC Interconnect IP is a configurable and technology independent IP, built for easy customization and integration into any …
Non-Coherent Network-on-Chip (NOC)
Performance (bandwidth and latency) optimized non-coherent NOC solution that significantly reduces silicon wire utilization, resu…
Scalable Mesh for Intelligent Connected Systems The Arm CoreLink CMN-700 Coherent Mesh Network is designed for intelligent connec…
The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped…
Included at no additional charge with Vivado and ISE Design Suite.
Coherent Network-on-Chip (NOC)
Scalable and area efficient interconnect solution optimized for memory coherent systems
Included at no additional charge with Vivado and ISE Design Suite The AXI Interconnect IP connects one or more AXI memory-mapped …
AXI system Peripheral IP, AXI Bus System Interconnect, Soft IP
AXI bus interconnect.