PCIe 7.0 Retimer Controller with CXL Support
PCI Express® (PCIe®) 7.0 links operating at 128 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions o…
- Controller
- PCIe 7.0
PCI Express (PCIe) IP cores enable high-speed serial communication between components in modern SoC and ASIC designs, delivering scalable bandwidth and low-latency connectivity.
These IP cores support multiple generations including PCIe Gen3, Gen4, Gen5, and Gen6, and include controller, PHY, endpoint, and root complex implementations.
This catalog allows you to compare PCIe IP cores from leading vendors based on data rate, latency, power efficiency, and process node compatibility.
Whether you are designing data center systems, AI accelerators, storage platforms, or high-performance computing systems, you can find the right PCIe IP for your connectivity requirements.
PCIe 7.0 Retimer Controller with CXL Support
PCI Express® (PCIe®) 7.0 links operating at 128 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions o…
The PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations.
The PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations.
Unlock High-Speed Data Transfer Between SmartNICs and Host CPU The ULL PCIe DMA Controller is a high-performance, bidirectional d…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
IP Prototyping Kits for USB, DDR, MIPI, PCI Express protocols
The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a , out-of-the-box reference design that c…
High Channel Count DMA IP Core for PCI-Express
The High Channel Count (HCC) DMA IP core for PCI-Express is a PCIe Endpoint with multiple industry standard AXI Interfaces.
iWave provides the user application for PCI-e target bridge to access the control & status registers of custom logic and data tra…
Multi-Channel Flex DMA IP Core for PCI Express
The Multi-Channel DMA IP Core for PCI-Express is a PCIe Endpoint with multiple industry standard AXI Interfaces.
PCIe PHY and controller solution
Brite 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance.
Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-effic…
PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5…
Compliant to PCI Express base specification 5.0
The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect va…
Scalable Switch Intel® FPGA IP for PCI Express
The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream…
Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller I…
The F-Tile Intel® Hard IP supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL…
Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP
Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is complia…
Multichannel DMA Intel FPGA IP for PCI Express*
The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applica…