CXL Host Device Dual mode controllers
Primesoc's CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.
- CXL
- Matured- FPGA validated
- Immediate
- CXL Spec V1.1
CXL IP cores enable high-speed serial connectivity for bandwidth-intensive systems in modern SoC and ASIC designs.
These IP cores support cache-coherent high-bandwidth connectivity for memory expansion, accelerators, and data-center-class compute fabrics, helping designers build scalable, standards-based interconnect for infrastructure, storage, multimedia, or advanced embedded applications
This catalog allows you to compare CXL IP cores from leading vendors based on throughput, latency, power efficiency, and process node compatibility.
Whether you are designing data center platforms, AI accelerators, memory expansion systems, or server SoCs, you can find the right CXL IP for your application.
CXL Host Device Dual mode controllers
Primesoc's CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.
CXL Controller With HPC Features (Spec Version 3.0 and Above)
Supports CXL 4.0 spec at 128GT/s and full backwards compatibility with CXL 3.x, 2.0, and 1.x
Hardware compressed memory IP for CXL devices and chip-to-chip links
Hardware compressed memory IP for CXL devices, with inline compression plus complete memory management
Comprehensive Portfolio of Device-Specific PCIe 7.0-CXL 4.0 IP
Controller + ATC + ATS + DTI · CXL.io · CXL.cache · CXL.mem · Memory pooling
Compliant with CXL Specification 2.0
Compute Express Link (CXL) FPGA IP
Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.
CXL - Enables robust testing of CXL-based systems for performance and reliability
CXL Verification IP is a cutting-edge solution for validating designs based on the Compute Express Link (CXL) protocol.
The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
The Cadence® Verification IP (VIP) for Compute Express Link (CXL) is part of the Cadence family of VIP for PCI Express® (PCIe®).
Adds security Interfaces, features to CXL 3.0 Premium controllers
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
Two-Digit Nanosecond PCIe 7.0-CXL 4.0 Link Controller IP
CXL Controller (Spec Version 2.0 and Below)
The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…
CXL 3.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…