SPI / QSPI / xSPI IP cores enable standards-based low-speed control and peripheral communication in modern SoC and ASIC designs.
These IP cores support serial peripheral communication and high-throughput Flash or peripheral access across standard and extended SPI variants, helping designers integrate interoperable control links across embedded, automotive, industrial, and connectivity-focused systems
This catalog allows you to compare SPI / QSPI / xSPI IP cores from leading vendors based on feature set, latency, power consumption, and process node compatibility.
Whether you are designing boot and storage paths, embedded peripherals, automotive systems, or industrial controllers, you can find the right SPI / QSPI / xSPI IP for your application.
AHB Quad SPI Controller with Execute in Place (XIP)
The Quad Serial Peripheral Interface module either controls a serial data link as a master component, or reacts to a serial data …
The SPI to AHB Lite Bridge IP core is commonly used as a monitor interface to allow external devices to access the internal AHB b…
AHB Octal SPI Controller with PSRAM and XIP Support
The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, u…
AXI Quad SPI Controller with Execute in Place (XIP)
The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an cache …
SPI Slave Serial Interface Controller
The SPI_SLAVE IP Core is an SPI compliant slave interface controller.
SPI Master Serial Interface Controller
The SPI_MASTER IP Core is an SPI compliant serial interface controller capable of driving up to 16 different slave devices in ful…
The Serial Peripheral Interface or SPI-bus is a simple 4- wire serial communications interface used by many peripheral chips that…
Quad SPI Flash Memory Controller
The SPI-MEM-CTRL core is an SPI serial NOR and serial NAND flash memory controller, supporting Single, Dual and Quad I/O SPI acce…
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI sla…
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master.
Arasan’s xSPI/PSRAM interface PHY is designed to work with both the xSPI or PSRAM master host controller IPs.
The SPI (Serial Peripheral Interface) is a specialized communication interface targeting single, dual or quad SPI Flash memories.
The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.
The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs.
The SafeSPI is a secure version of the SPI protocol that has been designed to provide enhanced security features, making it suita…
The SPI protocol specification supports high speed data transfer as per the peripheral specification, making it ideal for high - …
xSPI Multiple Bus Memory Controller
The industry ‘defacto standard’ memory controller for xSPI-like memories: HyperBus™ 1.0, 2.0 and 3.0 – OctaBus™ – Xccela® Bus – O…
SPI - Verifies reliable data transfer and protocol compliance in SPI systems
SPI (Serial Peripheral Interface) is a high-speed, synchronous communication protocol that ensures reliable data transfer between…
SPI Flash Controller - Ensures reliable validation of SPI Flash memory controllers
The SPI Flash Controller Verification IP (VIP) is a tool for verifying and simulating SPI Flash memory controllers in SoCs.
xSPI in production since 2019 for many production designs.The Cadence® Memory Model Verification IP (VIP) for xSPI provides verif…