Vendor: Silvaco, Inc. Category: SPI / QSPI XSPI

AXI Quad SPI Controller with Execute in Place (XIP)

The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an cache …

Overview

The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache architecture. This architecture enhances system performance, scalability, power efficiency, data locality, application responsiveness, cost optimization, and market competitiveness, providing a distinctive business value.

Key features

  • AMBA AXI interface
  • Execute-in-place (XIP) functionality for several industry-standard FLASH devices
  • DMA Interface
  • Software programmable Master component or Slave component mode
  • Software programmable SCLK rate for Master component mode
  • Quad and Dual-bit mode operation
  • 4-bit to 32-bit serial transmit & receive – 1 bit increments
  • Full and Half operation
  • Separate SCLK input for Master component Mode
  • 8 to 256 word Transmit and Receive FIFOs - configurable
  • Asynchronous Slave component Interface
  • Interrupt control
  • LSB or MSB mode
  • Up to 4 Slave components under Master component control

Block Diagram

AXI Quad SPI Controller with Execute in Place (XIP) block diagram

What’s Included?

  • Verilog Source
  • Complete Test Environment
  • AXI Bus Functional Model

Specifications

Identity

Part Number
70105
Vendor
Silvaco, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Silvaco, Inc.
HQ: United States

Learn more about SPI / QSPI XSPI IP core

Silvaco to Accelerate Physics-Based Digital Twins for Semiconductor Design and Manufacturing Using NVIDIA AI and Accelerated Computing

Silvaco is combining decades of physics-based modeling expertise with NVIDIA’s accelerated computing, CUDA-X™ libraries, PhysicsNeMo, Omniverse libraries, and Nemotron open models to help customers build, train, and deploy high-fidelity digital twins capable of predicting, optimizing, and validating complex semiconductor systems with unprecedented speed and accuracy.

Silvaco Reports Fourth Quarter and Full-Year 2025 Financial Results

Secured second artificial intelligence-driven machine learning (AI/ML) FTCO™ customer, driving revenue above high end of guided range. Executing cost reduction strategies ahead of expectations, resulting in operating expenses below midpoint of guided range. Q4’25 operating loss less than anticipated and cash burn, excluding one-time items, to reduce dramatically in Q1’26

Frequently asked questions about SPI / QSPI / xSPI IP cores

What is AXI Quad SPI Controller with Execute in Place (XIP)?

AXI Quad SPI Controller with Execute in Place (XIP) is a SPI / QSPI XSPI IP core from Silvaco, Inc. listed on Semi IP Hub.

How should engineers evaluate this SPI / QSPI XSPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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