SPI Slave Serial Interface Controller

The SPI_SLAVE IP Core is an SPI compliant slave interface controller. The controller decodes the bus signals and de-serializes them into a series of 8-bit bytes. Communication with the slave controller is achieved by programming a single control register and a single address register. The control register defines whether the transfer is a read or write and also the type of register to be accessed (config or status). The address register provides an index into the chosen register bank.

Both the config registers and the status registers are directly connected to the external ports of the controller. The config registers provide general purpose read/write bits for the control of an external device. The status registers are read only and allow the state of external pins to be monitored via the SPI interface.

All inputs to the slave interface controller are driven by the bus Master with the exception of miso which is a tristate output. The signal miso is normally in the high-impedance state unless a read operation is in active progress. The SPI slave controller is comprised of three main blocks as described by Figure 1. These blocks are the SPI Slave Controller core, the Configuration register bank and the Status register bank.

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• Synthesizable, technology independent IP Core for FPGA, ASIC and SoC
• Supplied as human readable VHDL (or Verilog) source code
• SPITM serial-bus compliant (including Motorola and TI modes)
• Simple programming makes use of a single control register and a single address register
• Architecture allows sustained 8-bit read/write operations
• User-defined number of 8-bit read-write configuration registers and 8-bit read-only status registers (up to 256 of each type)
• User-defined preset default values for all configuration registers
• Configurable clock polarity setting (CPOL)
• Configurable clock phase setting (CPHA)
• SPI bus signals are treated asynchronously in relation to the system clock
• Support of system clock to SPI clock ratios of 6:1 (or higher)
• Typical data rates of 50 Mbps+ on basic FPGA devices1

• SPI slave communications
• Inter-chip board-level communications
• Robust communication at higher data rates than other serial protocols such as I2C, UART and USB 1.X