SMBus Verification IP
The SMBus Verification IP provides an effective & efficient way to verify the components interfacing with SMBus interface of an I…
Overview
The SMBus Verification IP provides an effective & efficient way to verify the components interfacing with SMBus interface of an IP or SoC. The SMBus VIP is fully compliant with Rev. 3.3.1 of SMBus specifications. This VIP is a lightweight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.
Key features
- Fully compliant with Rev. 3.3.1 of the SMBus Specification.
- Support PEC (Packet error Checking) for communication robustness.
- Support for all Bus protocols with and without PEC.
- Support for SMBus ARP (Address Resolution Protocol) for dynamically assigning a unique address to each slave device.
- Support for Clock Synchronization & Arbitration for Multi Master.
- Supports Host device (specialized master) for SMBus Host Notify protocol.
- SMBALERT# interrupt line for devices that want to trade their ability to master for a pin.
- Supports generation of transactions with UVM register model.
- Built in SMBus Bus Monitor provides extensive protocol checking.
- Supports various error injection and detection.
- Provides verification scalability using functional coverage.
- Supports timing checks in the Monitor.
- Callbacks for user-defined transfers.
- Supports transaction logging with detailed description of each transfer.
- Graphical analyzer to show transactions for easy debugging
Block Diagram
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest level of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy integration in IP and SoC environment.
What’s Included?
- SMBus Master / Slave Agent
- SMBus Monitor and Scoreboard
- Test environment and Test suite
- Basic and directed protocol tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about I2C / I3C IP cores
What is SMBus Verification IP?
SMBus Verification IP is a I2C / I3C IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.