Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: PLL

High Speed PLL

This PLL IP is a programmable Analog PLL suitable for high speed clock generation.

Overview

This PLL IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By proper configurations to different values according to different FREF, CLK will be locked at the multiples of input frequency. CLKO is CLK divided by DP.
 

The output clock has excellent jitter performance, and can be used as high speed clock generator in SoCs and provide clock for high accuracy ADC converters.

Key features

  • Silicon proven in 22, 28, 40, 55, 65, 110, 130, 180nm from SMIC, HHgrace, GlobalFoundries and Samsung.
  • Support integer mode, Fraction mode and Spread-Spectrum mode
  • Input reference range:10MHz~100MHz
  • VCO frequency range:
    •   800~3200MHz                        
  • Core Area:0.0678 mm^2  
  • Output VCO clock period jitter peak –peak value :+/-2.5% of output period
  • Internal Post-divider to provide wide range output frequency
  • Power consumption, current on AVDD:
    •   1mA typ@FVCO=1GHz,                       
    •   4mA typ@FVCO=3GHz

Block Diagram

High Speed PLL block diagram

Specifications

Identity

Part Number
High Speed PLL
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

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Frequently asked questions about PLL IP cores

What is High Speed PLL?

High Speed PLL is a PLL IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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