Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: PLL

High Speed PLL

This PLL IP is a programmable Analog PLL suitable for high speed clock generation.

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Overview

This PLL IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By proper configurations to different values according to different FREF, CLK will be locked at the multiples of input frequency. CLKO is CLK divided by DP.
 

The output clock has excellent jitter performance, and can be used as high speed clock generator in SoCs and provide clock for high accuracy ADC converters.

Key features

  • Silicon proven in 22, 28, 40, 55, 65, 110, 130, 180nm from SMIC, HHgrace, GlobalFoundries and Samsung.
  • Support integer mode, Fraction mode and Spread-Spectrum mode
  • Input reference range:10MHz~100MHz
  • VCO frequency range:
    •   800~3200MHz                        
  • Core Area:0.0678 mm^2  
  • Output VCO clock period jitter peak –peak value :+/-2.5% of output period
  • Internal Post-divider to provide wide range output frequency
  • Power consumption, current on AVDD:
    •   1mA typ@FVCO=1GHz,                       
    •   4mA typ@FVCO=3GHz

Block Diagram

High Speed PLL block diagram

Specifications

Identity

Part Number
High Speed PLL
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is High Speed PLL?

High Speed PLL is a PLL IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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