Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: PLL

GSMC 0.18um 1.8v APLL

The GSMC18_PLL_01 is developed as a macro cell for clock generation.

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Overview

The GSMC18_PLL_01 is developed as a macro cell for clock generation. It can generate a stable high-speed clock from a slower clock signal. The output frequency is adjustable and can be up to 400MHz. The GSMC18_PLL_01 integrates a phase frequency detector (PFD), a low pass filter (LPF), a voltage controlled oscillator (VCO) and other associated supporting circuitry. All fundamental building blocks as well as fully programmable dividers are integrated in the core. It is useful for click multiplication of stable crystal oscillator sources and for de-skew clock signals.

Key features

  • Technology: GSMC18_PLL_01 is a 1P3M layout structure based on GSMC 0.18um 1P6M 1.8V logic process.
  • Single power supply: 1.8V
  • Input clock frequency range from 2MHZ to 50MHZ.
  • Output clock frequency range from 25MHZ to 400MHZ.
  • Low jitter

Specifications

Identity

Part Number
GSMC18_PLL_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about PLL IP core

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Frequently asked questions about PLL IP cores

What is GSMC 0.18um 1.8v APLL?

GSMC 0.18um 1.8v APLL is a PLL IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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