S2C Named Andes Technology’s 2026 Partner of the Year
本月，头部数字EDA企业思尔芯宣布，荣获RISC-V处理器IP领导厂商Andes晶心科技（Andes Technology）颁发的“2026年度最佳合作伙伴”奖项。该荣誉旨在表彰思尔芯在RISC-V生态共建、原型验证平台支撑及联合市场拓展中与Andes晶心深度协同、持续创造客户价值的突出表现。
Vendor:
Andes Technology Corp.
Category:
CPU
Full-featured Real-time Application Processor
The mid-range Andes Technology N10 processor is ideal for applications ranging from consumer media players and smart glasses all …
Overview
The mid-range Andes Technology N10 processor is ideal for applications ranging from consumer media players and smart glasses all the way to touch panel processing, motor control, and power management. The N10 features a 5-stage pipeline and operates at over 800 MHz clock rate providing plenty of performance for automotive electronics and industrial control. It also comes with I/D cache or local memory options that enable the core to more efficiently perform for networking or communication applications.
In the fast growing IoT market, the highly performance efficient N10 processor can be used as IoT gateway to bridge those ZigBee, Bluetooth or WiFi sensor devices to the internet connectivity. In addition, with the tightly-coupled IEEE-754 compliant NCESFP100 single-precision floating point unit (FPU), the N10 processor can be used in the high precision sensor devices to manipulate the data from ADC which converts physical continuous sensor signals to digital data.
In the fast growing IoT market, the highly performance efficient N10 processor can be used as IoT gateway to bridge those ZigBee, Bluetooth or WiFi sensor devices to the internet connectivity. In addition, with the tightly-coupled IEEE-754 compliant NCESFP100 single-precision floating point unit (FPU), the N10 processor can be used in the high precision sensor devices to manipulate the data from ADC which converts physical continuous sensor signals to digital data.
Key features
- Caches for fast code and data accesses
- Local Memories for deterministic code and data accesses
- IEEE754-compliant FPU coprocessor
- Memory Protection Unit (MPU) for secure RTOS
- Memory Management Unit (MMU) for Linux
Block Diagram
AndesCore™ N1068A block diagram
Benefits
- Performance
- Highly compact program size through AndeStar™ V3 ISA
- Single-cycle latency for most of 32-bit operations
- Extensive branch predictions (BTB and RAS) to speed up branch control
- MMU and MPU for memory management
- Zero-wait-state local memory with 1D/2D DMA for mass data transfer efficiently
- Flexibility
- All-C Embedded Programming
- Stack protection hardware to help determining stack size needed, and detect runtime overflow error
- Processor state bus to simply SoC design and debugging
- Support boot-up from instruction local memory
- Power Management
- Highly clock gating and logic gating
- Low power modes initiated by SW or SoC
- N:1 core vs. bus clock ratios
- PowerBrake technology to reduce peak power consumption
Applications
- Video event data recorder (VEDR)
- Wireless device
- Networking device
- Storage device
- DSC
- DVC
- Digital home
- Embedded controllerr
Specifications
Identity
Part Number
AndesCore™ N1068A
Vendor
Andes Technology Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
Learn more about CPU IP core
Andes Technology Honors Quintauris as 2026 Partner of the Year
This award recognizes Quintauris’ exceptional dedication to develop reference architectures and advancing mass-market commercialization for the RISC-V ecosystem with Andes.
Andes Technology Empowers RISC-V Developers with Its New Streamlined IDE, RVBuilder
Based on Visual Studio Code (VS Code), it is integrated, lightweight, and designed to streamline the development experience by bringing Andes’ industry-leading toolchain and advanced debugging capabilities directly into the most popular integrated development environment (IDE).
Andes Technology’s D23-SE RISC-V Processor Achieves ISO 26262 ASIL‑B and ASIL‑D Certification for Functional Safety Applications
Built upon the production-proven D23 architecture, the 32-bit D23-SE processor is specifically engineered for safety-critical systems requiring deterministic performance, robust security mechanisms, and accelerated SoC compliance workflow.
Andes Technology Unveils Next-Generation AI Solutions: AndesAIRE™ AnDLA™ I370 v2.0 and NN SDK v1.2.0 for Advanced ViT, VLM, and SLM at the Edge
This milestone release addresses one of the industry’s most challenging hurdles: enabling resource-heavy Transformer architectures such as Vision Transformers (ViT), Vision-Language Models (VLMs), and Small Language Models (SLMs) to execute efficiently on power- and cost-constrained edge platforms.
Andes Technology and Mirabilis Design Announce Collaboration on System-Level Models for Andes RISC-V Processor IP
Validated Architecture Models Enable Early Design Exploration and Pre-RTL Optimization
Frequently asked questions about CPU IP cores
What is Full-featured Real-time Application Processor?
Full-featured Real-time Application Processor is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.