Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 12-Track Standard POWERSLASH Core Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/LVT process 12-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/HVT process 12-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 9-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process
UMC 0.13um LL FSG Logic process high density POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process FSC0H_J POWERSLASHKit core Library.
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um SP/FSG process
UMC 0.13um SP FSG Logic process high density POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/LL process
UMC 0.11um eFlash/LL process 8-Track Cell Library.
Standard Cell PowerSlash(TM) Library IP, UMC 0.11um LL/FSG process
UMC 0.11um LL/FSG Logic process high density POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, 7 tracks, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process high density POWERSLASH (POWERSLASH) Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash/HS process 8-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K Logic process UHS Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm eHV process
UMC 55nm HV/HVT Low-K Logic process high speed Standard Core Library.