Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process
UMC 0.13um LL/FSG Logic process Mini-Library+.
- UMC
- 130nm
- LL
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process
UMC 0.13um LL/FSG Logic process Mini-Library+.
Standard Cell (High Voltage) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process 3.3V Device Core Cell Library for RTC/PMU usage.
Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.13um eHV process
UMC 0.13um Embedded High Voltage 1.5V Core Cell Library.
Standard Cell (Generic) Library IP, RVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 8-Track Generic Core Cell Library.
Standard Cell (Generic) Library IP, LVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 8-Track Generic Core Cell Library.
Standard Cell (Generic) Library IP, HVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 8-Track Generic Core Cell Library.
Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 12-Track high speed Generic Core Cell Library (C50).
Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 12-Track high speed Generic Core Cell Library (C40).
Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 12-Track high speed Generic Core Cell Library (C50).
Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 12-Track high speed Standard Core Cell Library.
Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 12-Track high speed Generic Core Cell Library (C50).
Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 12-Track high speed Generic Core Cell Library (C40).
Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (C50 Generic Core).
Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (Generic Core).
Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 9-Track Standard Cell Library (C50 Generic Core).
Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 9-Track Standard Generic Core Cell Library.
Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 9-Track Standard Cell Library (C50 Generic Core).
Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 9-Track Standard Cell Library (Generic Core).
Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 12-Track Standard Generic Core Cell Library (C38).
Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 12-Track Standard Cell Library (C35).