Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process
Faraday Technology
•
HQ:
Taiwan
UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library.
- UMC
- 55nm
- SP
Compare 2,955 UMC IP Cores from 31 vendors
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Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process
Faraday Technology• HQ: TaiwanUMC 55nm SP/HVT Logic process 7-Track POWERSLASH Cell Library.
- UMC
- 55nm
- SP
-
Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm SP process
Faraday Technology• HQ: TaiwanUMC 55nm SP/HVT Low-K process POWERSLASH Cell Library.
- UMC
- 55nm
- SP
-
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process
Faraday Technology• HQ: TaiwanUMC 55nm LP/RVT Low-K Logic process 12-Track POWERSLASH Core Cell Library.
- UMC
- 55nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 55nm LP process
Faraday Technology• HQ: TaiwanUMC 55nm LP/LVT Low-K Logic process 12-Track POWERSLASH Core Cell Library.
- UMC
- 55nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process
Faraday Technology• HQ: TaiwanUMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library.
- UMC
- 55nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 55nm LP process
Faraday Technology• HQ: TaiwanUMC 55nm LP/LVT Low-K Logic process 7-Track POWERSLASH Core Cell Library.
- UMC
- 55nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm LP process
Faraday Technology• HQ: TaiwanUMC 55nm LP/HVT Low-K Logic process 7-Track POWERSLASH Cell Library.
- UMC
- 55nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, RVT, 8 tracks, UMC 55nm LP process
Faraday Technology• HQ: TaiwanUMC 55nm LP/RVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
- UMC
- 55nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, LVT, 8 tracks, UMC 55nm LP process
Faraday Technology• HQ: TaiwanUMC 55nm LP/LVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
- UMC
- 55nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm LP process
Faraday Technology• HQ: TaiwanUMC 55nm LP/HVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
- UMC
- 55nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/RVT Low-K Logic process 7-Track POWERSLASH Cell Library.
- UMC
- 40nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/RVT Logic process 12-Track high speed POWERSLASH Cell Library (C40).
- UMC
- 40nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/LVT Logic process 12-Track high speed POWERSLASH Core Cell Library.
- UMC
- 40nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/HVT Logic process 12-Track high speed Cell POWERSLASH Library (C40).
- UMC
- 40nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/LVT Low-K Logic process 7-Track POWERSLASH Cell Library.
- UMC
- 40nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/HVT Low-K Logic process 7-Track POWERSLASH Cell Library.
- UMC
- 40nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (POWERSLASH Core).
- UMC
- 40nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/LVT Logic process 9-Track Standard Cell Library (POWERSLASH Core).
- UMC
- 40nm
- LP
-
Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/HVT Logic process 9-Track Standard Cell Library (POWERSLASH Core).
- UMC
- 40nm
- LP