A/D Converter IP, 10 bits, 45Msps, UMC 40nm LP process
1.1V/3.3V 10-Bit 45MSPS Pipelined Analog-to-Digital converter, UMC 40nm LP/RVT Low-K Logic process.
- 10 Bit
- UMC
- 40nm
- LP
A/D Converter IP, 10 bits, 45Msps, UMC 40nm LP process
1.1V/3.3V 10-Bit 45MSPS Pipelined Analog-to-Digital converter, UMC 40nm LP/RVT Low-K Logic process.
A/D Converter IP, 8 bits, 70Ksps, UMC 55nm SP process
8-Bit 70KSPS SAR Analog-to-Digital converter, UMC 55nm SP/RVT Low-K Logic process.
A/D Converter IP, 6 bits, 44Msps, UMC 0.25um MS process
6-Bit 44MSPS Differential Analog-to-Digital converter, UMC 0.25um Mixed-Mode process.
A/D Converter IP, 6 bits, 44Msps, UMC 0.18um Mixed-Mode process
6-Bit 44MSPS Differential Analog-to-Digital converter, UMC 0.18um Logic/Mixed-Mode process.
A/D Converter IP, 10 bits, 50Msps, UMC 40nm LP process
10-Bit 50MSPS SAR Analog-to-Digital converter, UMC 40nm LP/ Low-K LVT process.
A/D Converter IP, 10 bits, 2Msps, with 2-to-1 input MUX, UMC 55nm SP process
10-Bit 2MSPS SAR Analog-to-Digital converter with 2-to-1 Mux in, UMC 55nm SP/RVT process.
A/D Converter IP, 10 bits, 1Msps, UMC 0.18um G2 process
10-Bit 1MSPS single-end Analog-to-Digital converter, UMC 0.18um GII Logic process.
A/D Converter IP, 10 bits, 167Ksps, UMC 55nm SP process
A 1.8V, 10-Bit 167KSPS 8-to-1 Low Power SAR Analog-to-Digital converter with internal temperature sensor, UMC 55nm SP/RVT Logic p…
PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
Metal Programmable IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process
UMC 0.18um GII Logic process True 1.8V Metal-programmable IO (MPIO) Cell Library.
10/100 Ethernet PHY IP, UMC 90nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 90nm SP/RVT Low-K Logic process.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process
UMC 90nm SP/HVT Low-K process POWERSLASH Core Cell Library libary.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process Low Power standard Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process
UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version).
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process
UMC 65nm SP/HVT process POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm LL process
UMC 65nm LL/HVT Low-K Logic process POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library POWERSLASHKit.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells.