UMC IP Cores

Input 5M-100MHz, output 62.5M-1000MHz, frequency synthesizable PLL with power/ground pad, UMC 0.13um HS/FSG Logic process.

• UMC
• 130nm
• HS

Input 5M-100MHz, output 62.5M-1000MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.

• UMC
• 130nm
• HS

Input 5M-100MHz, output 20M-300MHz, frequency synthesizable PLL, 0.25um Logic process.

• UMC
• 250nm

Input 4M-200MHz, output 20M-400MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.

• UMC
• 180nm
• G

Input 45k-60KHz, output 81M- 132MHz, PLL, UMC 0.11um HS/FSG Logic process.

• UMC
• 110nm
• HS

UMC 0.13um HS/FSG process PLL for DDR2.

• UMC
• 130nm
• HS

Input 25M-50MHz, output 1000M-2000MHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HPM process.

• UMC
• 28nm
• HPM

Input 25M-200MHz, output 1000M-1500MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.

• UMC
• 90nm
• SP

Input 20M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HPM process.

• UMC
• 28nm
• HPM

Input 20M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 28nm Logic and Mixed-Mode HLP process.

• UMC
• 28nm
• HLP

Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.

• UMC
• 130nm
• HS

Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.11um HS/AE (AL Enhancement) Logic process.

• UMC
• 110nm
• HS

Input 20M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.

• UMC
• 180nm
• G

Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output frequency synthesizable PLL, UMC…

• UMC
• 28nm
• HPM

Half low pass filter area compare with FXPLL362HJ0G, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400M…

• UMC
• 28nm
• HPM

Input 1M-300MHz, output 20M-300MHz, frequency synthesizable PLL, 0.18um GII Logic process.

• UMC
• 180nm
• G

Input 1M-200MHz, output 25M-380MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.

• UMC
• 180nm
• G

Input 12MHz, output clock1 540MHz and output clock2 120MHz, PLL, UMC 40nm LP/RVT Low-K Logic process.

• UMC
• 40nm
• LP

Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 90nm SP Logic process.

• UMC
• 90nm
• SP

miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 250MHz and 500MHz, UMC 40nm LP/RVT Logic proces…

• UMC
• 40nm
• LP