Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
- UMC
- 130nm
- HS
Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm SP process
Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for Ji…
Oscillator IP, Output: 5KHz, UMC 55nm SP process
Output frequency 5KHz.
One Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm SP/RVT low_K Logic process synchronous One Port Register File.
One Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm Logic standard performance process synchronous high density Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 55nm eFlash process
UMC 55nm eFlash One Port Register File with Power Gating.
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP One Port Register File with Sleep/Retention/Nap mode & peripheral LVT feature.
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP One Port Register File with Sleep/retention/Nap mode feature.
One Port Register File Compiler IP, UMC 28nm SP process
UMC 28nm Logic process synchronous Ultra high speed Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process One Port Register File with LVT.
One Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K One Port Register File.
One Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/UHS One Port Register File compiler with peripheral LVT.
One Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.18um LL process
UMC 0.18um LL Logic process synchronous Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.13um SP process
UMC 0.13-micron 1.2V high speed (HS) Logic process synchronous Low Power Single Port Register File SRAM compiler.