UMC IP Cores

UMC 0.13um LL Logic/FSG process high density synchronous Single Port Register File SRAM memory compiler.

• UMC
• 130nm
• LL

UMC 0.13um HS/FSG Logic process synchronous Single Port Register File SRAM memory compiler.

• UMC
• 130nm
• HS

UMC 0.13um HS/LL fusion (FSG) process high density synchronous Single Port Register File SRAM memory compiler.

• UMC
• 130nm
• HS

UMC 0.11um LL/FSG process synchronous Single Port Register File SRAM memory compiler.

• UMC
• 110nm
• LL

UMC 0.11um HS Logic process synchronous Single Port Register File memory compiler.

• UMC
• 110nm
• HS

UMC 0.11um HS/FSG Logic process, One Port Register File memory compiler.

• UMC
• 110nm
• HS

UMC 0.11um HS/AE (AL Enhancement) Logic process synchronous high density Single Port Register File SRAM memory compiler.

• UMC
• 110nm
• HS

UMC 55um LP Low-K process One Port Register File compiler.

• UMC
• 55nm
• LP

MIPI Transmitter 80Mbps~1.5Gbps, UMC 40nm LP/RVT/LVT Low-K process.

• MIPI D-PHY
• UMC
• 40nm
• LP

MIPI Transmitter 80Mbps~1.5Gbps with 1-clock lane, 2-data lanes, UMC 40nm LP/RVT/LVT Low-K process.

• MIPI D-PHY
• UMC
• 40nm
• LP

MIPI Transmitter 80~1500MHz with 1-clock lane, 4-data lanes, UMC 40nm LP/RVT/LVT Low-K process.

• MIPI D-PHY
• UMC
• 40nm
• LP

MIPI Transmitter 80Mbps~1500Mbps combo with CMOS input, UMC 40nm LP Low-K process.

• MIPI D-PHY
• UMC
• 40nm
• LP

MIPI Receiver 80Mbps-1.5Gbps, UMC 40nm LP Low-K Logic process.

• MIPI D-PHY
• UMC
• 40nm
• LP

Single Port LVDS Transmitter PAD 1.25Gbps, UMC 90nm SP/RVT Low-K process.

• UMC
• 90nm
• SP

LVDS RX IO PAD 500Mbps, UMC 55nm LP/RVT Low-K Logic process.

• UMC
• 55nm
• LP

3.3V to 1.0V/100mA REG, Linear Regulator, UMC 90nm SP/RVT Low-K Logic process.

• UMC
• 90nm
• SP

2.5V to 1.2V/100mA REG, Linear Regulator, UMC 90nm SP/RVT Low-K Logic process.

• UMC
• 90nm
• SP

3.3V to 1.1V/100mA REG, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.

• UMC
• 40nm
• LP

1.8V and 1.2V input, loading 360mA, 1.1V output with VBG=0.88V Regulator with BYPASS mode, UMC 40nm LP/RVT Low-K Logic process.

• UMC
• 40nm
• LP

3.3V to 1.8V with 150mA driving capability, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.

• UMC
• 40nm
• LP