UMC IP Cores

DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq.

• UMC
• 130nm
• HS

LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad.

• UMC
• 40nm
• LP

LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process

• UMC
• 40nm
• LP

Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process

• UMC
• 110nm
• HS

Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Proce…

• UMC
• 110nm
• HS

10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process

• UMC
• 28nm
• HPC+

0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.

• UMC
• 130nm
• HS

10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process

• UMC
• 28nm
• HPC

40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process

• Controller + PHY + 1
• UMC
• 40nm
• LP

LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process

• Controller + PHY + 1
• UMC
• 40nm
• LP

40nm LPDDR2-PHY data block for SIP

• Controller + PHY + 1
• UMC
• 40nm
• LP

40nm LPDDR2-PHY command/address block for SIP

• Controller + PHY + 1
• UMC
• 40nm
• LP

40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage

• Controller + PHY + 1
• UMC
• 40nm
• LP

UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device

• Controller
• UMC
• 40nm
• LP

DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 40nm
• LP

DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process .

• Controller + PHY + 1
• UMC
• 40nm
• LP

DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process.

• Controller + PHY + 1
• UMC
• 40nm
• LP

DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 40nm
• LP

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP

UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage

• Controller + PHY + 1
• DDR2
• UMC
• 55nm
• SP