Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process
- UMC
- 55nm
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Enhancement) Logic Process
Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process
Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process
Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RV…
Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Enhancement) Logic Process
Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process
Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process
Input 2M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process
Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process
Internal-RC, trimmable fixed frequency 80MHz.
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz.
Output frequency 32KHz. Input 0.9V-1.1V; UMC 55nm SP/RVT LowK Logic Process
Output frequency 32KHz.
Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process
Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process
internal-R, frequency 32.768MHz RC OSC. Input 0.9V±10% or 1.2V±10% ; UMC 55 nm EFLASH process
internal-R, frequency 32.768MHz RC OSC.
Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process
Internal-RC, frequency 8MHz.
XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process
XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process
Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process
Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process
1.2V 50-202.5MHz DLL with programable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process
1.2V 50-202.5MHz DLL with programable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process
Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process.
Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process.
Linear Regulator IP, UMC 0.18um G2 process
Input 2.7V~3.6V, Output=1.8V,Loading 50mA Regulator, UMC 0.18um GII 1.8V/3.3V Process
Standard Cell (Generic) Library IP, UMC 0.13um process
UMC 0.13um Logic process, DFY Cell Library.