UMC IP Cores

1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process

• UMC
• 28nm
• HPC

100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process

• UMC
• 130nm
• HS

100MHz single-ended to differential clock buffer for UMC 40nm LP.

• UMC
• 40nm
• LP

LVDS Transmitter 700Mbps; UMC 28nm HPC Process

• UMC
• 28nm
• HPC

2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process.

• UMC
• 40nm
• LP

3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces

• UMC
• 28nm
• HPC

The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process

• UMC
• 40nm
• LP

The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process

• UMC
• 55nm
• LP

The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process

• UMC
• 55nm

The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process

• UMC
• 40nm
• LP

LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip

• UMC
• 40nm
• LP

LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process

• UMC
• 55nm

3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process

• UMC
• 40nm
• LP

8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process

• UMC
• 40nm
• LP

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process

• UMC
• 55nm
• SP

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process

• UMC
• 55nm
• SP

Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Enhancement) Logic Process

• UMC
• 110nm
• HS

UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format

• UMC
• 28nm
• HPC+

3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process

• UMC
• 40nm
• LP

DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process

• UMC
• 130nm
• HS