The Platform Based SOC Design that Utilizes Structured ASIC Technology
The Platform Based SOC Design that Utilizes Structured ASIC Technology
DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq.
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 130nm | HS | — |
DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process is a DLL IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DLL IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.