DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process
- Controller + PHY + 1
- DDR3
- UMC
- 40nm
- LP
DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Log…
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
High performance 8-bit micro-controller
High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counter, and two 16-bit dptr; UMC 0.1…
Video Encoder/Decoder -- MPEG-4 (ISO/IEC 14496-2) and JPEG (ISO/IEC 10918-1); UMC 0.13um HS/FSG
FTMCP100 is a video and image compression / decompresion IP core that supports the MPEG-4 (ISO/IEC 14496-2) and JPEG (ISO/IEC 109…
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synt…
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process