USB 2.0 PHY IP, Silicon Proven in TSMC 65LP
A physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
USB 2.0 PHY IP, Silicon Proven in TSMC 55LP
In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed.
USB 2.0 PHY IP, Silicon Proven in TSMC 12FFC
The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 7FF
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 3.0 PHY IP, Silicon Proven in TSMC 55LP
For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered.
USB 3.0 PHY IP, Silicon Proven in TSMC 40LP
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.
USB 3.0 PHY IP, Silicon Proven in TSMC 22ULP
The USB 3.0 PHY IP Core is a transceiver provided for supplementary devices, compliant with UTMI (USB SuperSpeed), USB 3.0, and U…
USB 3.0 PHY IP, Silicon Proven in TSMC 16FFC
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.
USB 3.0 PHY IP, Silicon Proven in TSMC 12FFC
For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
All USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps are supported by the USB 3.2 Gen2X1 transceiver IP.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
USB 3.0 PHY IP, Silicon Proven in TSMC 7FF
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 12FFC
All USB 3.2 Gen2X1 host and peripheral applications are supported up to 10Gbps by the USB 3.2 Gen2X1 transceiver IP.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 7FF
The USB 3.2 Gen2X1 transceiver IP offers all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps.
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in TSMC 28HPC+
For Gigabit 10/100/1000 Ethernet applications, the GPHY is a integrated single chip.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 40ULP
The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
The whole spectrum of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
A wide variety of PCIe 2.0 Base applications are available with PCIe 2.0 transceiver IP.
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
A comprehensive selection of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
The PCIe 3.0 PHY IP is designed to support increased applications with its low-power, multi-lane, high-performance design.