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Rising software complexity, tighter development timelines, and cost pressures require automotive companies to re-engineer how they design, deploy, and maintain their system architectures. Addressing these challenges requires an agile, collaborative approach to engineering — from silicon to systems — along with trusted partners capable of delivering powerful, integrated solutions.
In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
Rohan Bhatnagar, Staff Product Manager, Synopsys EDA Group
While the IP landscape will always look different when seen through the eyes of SOC designers, integrators and IP vendors, these players gain a significant advantage if they see each others’ roles more clearly. This article explores the perspectives of three such players and their different ways of working with IP with an eye to making life with IP easier for everyone.
This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
With the evolution of Internet of Things, the requirement for ultra-low power systems have increased. To design a low power system, we must apply all the possible low power methods at each level of the system implementation. Currently, most of the systems are designed by integrating off-the-shelf Digital and Analog Intellectual Property (IP) blocks. In this paper, we focus on achieving lower power for existing IPs and the importance of architecture level clock gating and EDA Tool inserted clock gating.
