Vendor: Synopsys, Inc. Category: PVT Monitor

Process Detector (For DVFS and monitoring process variation), TSMC 16FFC

An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability…

TSMC 16nm FFC Available on request View all specifications

Overview

An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS designs. The process detector provides the means to assess process variation from die to die and on chip variation across large die. Process detectors are especially useful in the bring up and characterization phase of new silicon, assessing and compensating for ageing and minimizing voltage guard bands through voltage scaling schemes. This In-Chip Sensing and PVT Monitoring IP is available as part of the Synopsys DesignWare® Foundation IP portfolio. It also forms the foundation of the new Synopsys Silicon Lifecycle Management (SLM) platform. SLM enables new levels of insight for both SoC providers as well as their customers to optimize operational activities at each stage of the device and system lifecycles from design to in-field.

Key features

  • Measurement of multiple device types
  • Support for custom delay chain structures
  • Signature Response on Demand
  • Scan-path Inserted
  • Fault coverage and test options
  • Created using standard digital process layers
  • Small size

Benefits

  • Process speed assessment & characterisation
  • Assess aging
  • Critical Voltage & Timing Analysis

Applications

  • In-die process speed detection
  • Age monitoring and compensation
  • Enabling voltage scaling schemes

What’s Included?

  • Datasheet
  • GDSII
  • LEF (Abstract) view
  • Liberty timing files
  • LVS netlist
  • Verilog model

Silicon Options

Foundry Node Process Maturity
TSMC 16nm FFC Available on request

Specifications

Identity

Part Number
dwc_sensors_pd_tsmc16ffc
Vendor
Synopsys, Inc.
Type
Silicon IP

Provider

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Frequently asked questions about PVT Monitor IP cores

What is Process Detector (For DVFS and monitoring process variation), TSMC 16FFC?

Process Detector (For DVFS and monitoring process variation), TSMC 16FFC is a PVT Monitor IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this PVT Monitor?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PVT Monitor IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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