Vendor: Pacific MicroCHIP Corp. Category: PLL

Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40

PMCC_PLL5GN40 is a PLL IP block which synthesizes low-jitter (

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TSMC 40nm G Silicon Proven View all specifications

Overview

PMCC_PLL5GN40 is a PLL IP block which synthesizes low-jitter (<0.3ps RMS) 4.96GHz to 5.6GHz (5.28GHz typical) clock signals from the 620-700MHz reference clock. The pseudo-differential CMOS outputs are aligned to have ±35ps skew over PVT. The block is powered from the 0.9V (core) and 1.8V supply voltages. Silicon proven on 2 ASICs. Can be modified as per customer specifications.

Key features

  • Low RJ output – 0.3ps RMS for the primary 5GHz output.
  • A built-in bandgap block for the generation of reference voltages/currents.
  • An output clock duty cycle within 50±3% range.
  • Jitter peaking <1dB.
  • The embedded FSM for the PLL auto-tune with a lock-detection indicator.
  • Power consumption of 25mW.
  • Total on-chip area 0.42mm2.

Benefits

  • The PLL IP block provides high-accuracy clock signals with predictable timing constrains.

Applications

  • Any ASIC in the TSMC 40G process.
  • Can be modified to fit any application.

What’s Included?

  • LEF view
  • Verilog (.v)
  • Liberty file (.lib)
  • GDSII
  • CDL/Spice netlist for LVS

Silicon Options

Foundry Node Process Maturity
TSMC 40nm G Silicon Proven

Specifications

Identity

Part Number
PMCC_PLL5GN40
Vendor
Pacific MicroCHIP Corp.
Type
Silicon IP

Provider

Contact Pacific MicroCHIP Corp.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40?

Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40 is a PLL IP core from Pacific MicroCHIP Corp. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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