Learn more about Comparator IP core
Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC (System on Chip). For such applications, the design of the “Always-On power domain" (a.k.a AON power domain) is pivotal.
In mobile electronics, a single device suffices to cover various daily usages: calling, taking pictures, playing music, geolocating, etc… All of these common features should fit in one’s hand. To adequately implement these new functionalities, audio electronics must not be limited to basic plug and play functionalities any longer. Smartphone applications should be compliant with new user practices by enabling more interactivity and giving more possibilities to control the inner functionalities.
This article explains step by step implementation of Median Filtering Algorithm in Verilog. This filtering technique is then applied to noisy image for denoising. This article also explains simple Verilog based testbench and Matlab scripts for image pre/post processing operation for verifying the same.
This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.
As the system, software & IP complexity is increasing so is the demand of SystemC models & Virtual Platform for verification. To achieve it, the key requirements are that the models/platform should be developed fast, reusable & highly accurate. We are sharing the experience of our company 3D-IP Semiconductors Ltd. for the development of a generic Virtual Platform using TLM 2.0; reusable for any system model.
