TSMC IP Cores

C-PHY/D-PHY Combo in various production nodes at low cost and power.

• MIPI D-PHY
• TSMC
• 40nm
• LP
• In Production

Several production nodes employ C-PHY/D-PHY Combo to consume the least amount of energy and funds.

• MIPI D-PHY
• TSMC
• 28nm
• HPC+
• In Production

C-PHY/D-PHY Combo at low cost and power in several manufacturing nodes.

• MIPI D-PHY
• TSMC
• 28nm
• HPC+
• In Production

In order to use the least amount of power and money, several production nodes use C-PHY/D-PHY Combo.

• MIPI D-PHY
• TSMC
• 22nm
• ULP
• In Production

C-PHY/D-PHY Combo in numerous process nodes at low cost and power.

• MIPI D-PHY
• TSMC
• 22nm
• ULP
• In Production

In order to use the least amount of power and money, several production nodes use C-PHY/D-PHY Combo.

• MIPI D-PHY
• TSMC
• 16nm
• FFC
• In Production

Low power and cost C-PHY/D-PHY Combo in multiple process nodes.

• MIPI D-PHY
• TSMC
• 16nm
• FFC
• In Production

Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.

• MIPI D-PHY
• TSMC
• 12nm
• FFC
• In Production

C-PHY/D-PHY Combo in various process nodes with low power and cost.

• MIPI D-PHY
• TSMC
• 12nm
• FFC
• In Production

Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.

• MIPI D-PHY
• TSMC
• 7nm
• N7FF
• In Production

Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.

• MIPI D-PHY
• TSMC
• 7nm
• N7FF
• In Production

The D-PHY specification, version 1.2, is fully complied with by the MIPI D-PHY Analog RX IP Core.

• MIPI D-PHY
• TSMC
• 40nm
• LP
• In Production

The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.

• MIPI D-PHY
• TSMC
• 40nm
• LP
• In Production

A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.

• TSMC
• 40nm
• G

The MIPI D-PHY RX IP Core fully adheres to the D-PHY specification, version 1.2.

• MIPI D-PHY
• TSMC
• 16nm
• FFC
• In Production

Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.

• MIPI D-PHY
• TSMC
• 12nm
• FFC
• In Production

C-PHY/D-PHY Combo in various process nodes with low power and cost.

• MIPI D-PHY
• TSMC
• 12nm
• FFC
• In Production

Various manufacturing nodes using C-PHY/D-PHY Combo at minimal cost and power.

• MIPI D-PHY
• TSMC
• 7nm
• N7FF
• In Production

Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.

• MIPI D-PHY
• TSMC
• 7nm
• N7FF
• In Production

The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.

• USB 2.0
• TSMC
• 90nm
• G
• In Production